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rev.1.00 jun 27, 2005 page 1 of 19 HM64YGB36100 series 32m synchronous late write fast static ram (1-mword 36-bit) rej03c0271-0100 (previous ade-203-1374 (z) rev. 0.0) rev.1.00 jun.27.2005 description the HM64YGB36100 is a synchronous fast static ram organized as 1-mword 36-bit. it has realized high speed access time by employing the most advanced cmos process and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. it is packaged in standard 119-bump bga. note: all power supply and ground pins must be connected for proper operation of the device. features ? 2.5 v 5% operation and 1.5 v (v ddq ) ? 32-mbit density ? synchronous register to register operation ? internal self-timed late write ? byte write control (4 byte write selects, one for each 9-bit) ? optional 18 configuration ? hstl compatible i/o ? programmable impedance output drivers ? differential hstl clock inputs ? asynchronous g output control ? asynchronous sleep mode ? fc-bga 119pin package with sram jedec standard pinout ? limited set of boundary scan jtag ieee 1149.1 compatible ordering information type no. organization access time cycle time package HM64YGB36100bp-33 1m 36 1.6 ns 3.3 ns 119-bump 1.27 mm 14 mm 22 mm bga prbg0119dc-a (bp-119f) note: hm: hitachi memory prefix, 64: external cache sram, y: v dd = 2.5 v, g: late write sram, b: v ddq = 1.5 v
HM64YGB36100 series rev.1.00 jun 27, 2005 page 2 of 19 pin arrangement 1 2 3 4 5 6 7 a v ddq sa14 sa13 nc sa6 sa7 v ddq b nc sa15 sa12 sa20 sa5 sa9 nc c nc sa16 sa11 v dd sa4 sa8 nc d dqc7 dqc8 v ss zq v ss dqb8 dqb7 e dqc5 dqc6 v ss ss v ss dqb6 dqb5 f v ddq dqc4 v ss g v ss dqb4 v ddq g dqc3 dqc2 swec nc sweb dqb2 dqb3 h dqc1 dqc0 v ss nc v ss dqb0 dqb1 j v ddq v dd v ref v dd v ref v dd v ddq k dqd1 dqd0 v ss k v ss dqa0 dqa1 l dqd3 dqd2 swed k swea dqa2 dqa3 m v ddq dqd4 v ss swe v ss dqa4 v ddq n dqd5 dqd6 v ss sa17 v ss dqa6 dqa5 p dqd7 dqd8 v ss sa19 v ss dqa8 dqa7 r nc sa10 m1 v dd m2 sa1 nc t nc nc sa18 sa3 sa2 nc zz u v ddq tms tdi tck tdo nc v ddq (top view) block diagram read add. reg. write add. reg. 1m 36 memory array ss reg. swe reg. output reg. din reg. sa1 to sa20 swe ss 1 0 k 1 0 sa1 to sa20 compare swex 1st reg. swex (x: a to d) swex 2nd reg. byte write control output enable dqxn (x: a to d, n: 0 to 8) match0 impedance control zq g
HM64YGB36100 series rev.1.00 jun 27, 2005 page 3 of 19 pin descriptions name i/o type descriptions notes v dd supply core power supply v ss supply ground v ddq supply output power supply v ref supply input reference, provides input reference voltage k input clock input, active high k input clock input, active low ss input synchronous chip select swe input synchronous write enable san input synchronous address input n: 1 to 20 swex input synchronous byte write enables x: a to d g input asynchronous output enable zz input power down mode select zq input output impedance control 1 dqxn i/o synchronous data input/output x: a to d n: 0 to 8 m1, m2 input output protocol mode select tms input boundary scan test mode select tck input boundary scan test clock tdi input boundary scan test data input tdo output boundary scan test data output nc ? no connection m1 m2 protocol notes v ss v dd synchronous register to register operation 2 notes: 1. zq is to be connected to v ss via a resistance rq where 175 ? rq 300 ? . if zq = v ddq or open, output buffer impedance will be maximum. 2. mode control input pins m1 and m2 are set at power-up and will not change the states during the sram operates. this sram supports only single clock, pipelined read protocol. other settings are not applicable. mode control pin m2 can be set to v ddq instead of v dd .
HM64YGB36100 series rev.1.00 jun 27, 2005 page 4 of 19 truth table zz ss ss ss ss g g g g swe swe swe swe swea swea swea swea sweb sweb sweb sweb swec swec swec swec swed swed swed swed k k k k k operation dq (n) dq (n+1) h sleep mode high-z high-z l h l-h h-l dead (not selected) high-z l h h dead (dummy read) high-z l l l h l-h h-l read d out (a, b, c, d) 0 to 8 l l l l l l l l-h h-l write a, b, c, d byte high-z d in (a, b, c, d) 0 to 8 l l l h l l l l-h h-l write b, c, d byte high-z d in (b, c, d) 0 to 8 l l l l h l l l-h h-l write a, c, d byte high-z d in (a, c, d) 0 to 8 l l l l l h l l-h h-l write a, b, d byte high-z d in (a, b, d) 0 to 8 l l l l l l h l-h h-l write a, b, c byte high-z d in (a, b, c) 0 to 8 l l l h h l l l-h h-l write c, d byte high-z d in (c, d) 0 to 8 l l l l h h l l-h h-l write a, d byte high-z d in (a, d) 0 to 8 l l l l l h h l-h h-l write a, b byte high-z d in (a, b) 0 to 8 l l l h l l h l-h h-l write b, c byte high-z d in (b, c) 0 to 8 l l l h h h l l-h h-l write d byte high-z d in (d) 0 to 8 l l l h h l h l-h h-l write c byte high-z d in (c) 0 to 8 l l l h l h h l-h h-l write b byte high-z d in (b) 0 to 8 l l l l h h h l-h h-l write a byte high-z d in (a) 0 to 8 notes: 1. h: v ih , l: v il , : v ih or v il 2. swe , ss , swea to swed and sa are sampled at the rising edge of k clock.
HM64YGB36100 series rev.1.00 jun 27, 2005 page 5 of 19 programmable impedance output drivers output buffer impedance can be programmed by terminating the zq pin to v ss through a precision resistor (rq). the value of rq is five times the output impedance desired. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is 250 ? typical. if the status of zq pin is open, output impedance is maximum value. maximum impedance also occurs with zq connected to v ddq . the impedance update of the output driver occurs when the sram is in high-z. write and deselect operations will synchronously switch the sram into and out of high-z, therefore will trigger an update. at power up, the output buffer is in high-z. it will take 4,096 cycles for the impedance to be completely updated. absolute maximum ratings parameter symbol rating unit notes input voltage on any pin v in ? 0.5 to v ddq + 0.5 v 1, 4 core supply voltage v dd ? 0.5 to +3.13 v 1 output supply voltage v ddq ? 0.5 to +2.1 v 1, 4 operating temperature t opr 0 to +85 c storage temperature t stg ? 55 to +125 c output short-circuit current i out 25 ma latch up current i li 200 ma package junction to top thermal resistance j-top 6.5 c/w 5 package junction to board thermal resistance j-board 12 c/w 5 notes: 1. all voltage is referenced to v ss . 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted the operation conditions. exposure to higher voltages than recommended voltages for extended periods of time could affect device reliability. 3. these cmos memory circuits have been designed to meet the dc and ac specifications shown in the tables after thermal equilibrium has been established. 4. the following supply voltage application sequence is recommended: v ss , v dd , v ddq , v ref then v in . remember, according to the absolute maximum ratings table, v ddq is not to exceed 2.1 v, whatever the instantaneous value of v ddq . 5. see figure below. j-top thermocouple thermo grease water cold plate sram teflon block jedec/2s2p bga thermal board thermocouple thermo grease water cold plate sram teflon block jedec/2s2p bga thermal board j-board water water
HM64YGB36100 series rev.1.00 jun 27, 2005 page 6 of 19 note: the following dc and ac specifications shown in the tables, this device is tested under the minimum transverse air flow exceeding 500 linear feet per minute. recommended dc operating conditions (ta = 0 to +85 c) parameter symbol min typ max unit notes power supply voltage: core v dd 2.38 2.50 2.63 v power supply voltage: i/o v ddq 1.40 1.50 1.60 v input reference voltage: i/o v ref 0.60 0.75 0.90 v 1 input high voltage v ih v ref + 0.10 ? v ddq + 0.30 v 4 input low voltage v il ? 0.30 ? v ref ? 0.10 v 4 clock differential voltage v dif 0.10 ? v ddq + 0.30 v 2, 3 clock common mode voltage v cm 0.60 ? 0.90 v 3 notes: 1. peak to peak ac component superimposed on v ref may not exceed 5% of v ref . 2. minimum differential input voltage required for differential input clock operation. 3. see figure below. 4. v ref = 0.75 v (typ). differential voltage / common mode voltage v dif v cm v ddq v ss
HM64YGB36100 series rev.1.00 jun 27, 2005 page 7 of 19 dc characteristics (ta = 0 to +85 c, v dd = 2.5 v 5%) parameter symbol min max unit notes input leakage current i li ? 2 a 1 output leakage current i lo ? 5 a 2 standby current i sbzz ? 150 ma 3 v dd operating current, excluding output drivers i dd ? 550 ma 4 quiescent active power supply current i dd2 ? 200 ma 5 maximum power dissipation, including output drivers p ? 2.3 w 6 parameter symbol min typ max unit notes output low voltage v ol v ss ? v ss + 0.4 v 7 output high voltage v oh v ddq ? 0.4 ? v ddq v 8 zq pin connect resistance rq ? 250 ? ? output ?low? current i ol (v ddq /2) / {(rq/5) ? 15%} (v ddq /2) / {(rq/5) + 15%} ma 9, 11 output ?high? current i oh (v ddq /2) / {(rq/5) + 15%} (v ddq /2) / {(rq/5) ? 15%} ma 10, 11 notes: 1. 0 v in v ddq for all input pins (except v ref , zq, m1, m2 pin) 2. 0 v out v ddq , dq in high-z 3. all inputs (except clock) are held at either v ih or v il , zz is held at v ih , i out = 0 ma. specification is guaranteed at +75 c junction temperature. 4. i out = 0 ma, read 50% / write 50%, v dd = v dd max, frequency = min. cycle 5. i out = 0 ma, read 50% / write 50%, v dd = v dd max, frequency = 3 mhz 6. output drives a 12 pf load and switches every cycle. this parameter should be used by the sram designer to determine electrical and package requirements for the sram device. 7. rq = 250 ? , i ol = 6.8 ma 8. rq = 250 ? , i oh = ? 6.8 ma 9. measured at v ol = 1/2 v ddq 10. measured at v oh = 1/2 v ddq 11. the total external capacitance of zq pin must be less than 7.5 pf.
HM64YGB36100 series rev.1.00 jun 27, 2005 page 8 of 19 ac characteristics (ta = 0 to +85 c, v dd = 2.5 v 5%) single differential clock register-register mode HM64YGB36100bp -33 parameter symbol min max unit notes ck clock cycle time t khkh 3.3 ? ns ck clock high width t khkl 1.3 ? ns ck clock low width t klkh 1.3 ? ns address setup time t avkh 0.3 ? ns 2 data setup time t dvkh 0.3 ? ns 2 address hold time t khax 0.6 ? ns data hold time t khdx 0.6 ? ns clock high to output valid t khqv ? 1.6 ns 1 clock high to output hold t khqx 0.65 ? ns 1, 6 clock high to output low-z ( ss control) t khqx2 0.65 ? ns 1, 4, 6 clock high to output high-z t khqz 0.65 2.0 ns 1, 3, 6 output enable low to output low-z t glqx 0.1 ? ns 1, 4, 6 output enable low to output valid t glqv ? 2.0 ns 1, 4 output enable high to output high-z t ghqz ? 2.0 ns 1, 3 sleep mode recovery time t zzr 20.0 ? ns 5 sleep mode enable time t zze ? 15.0 ns 1, 3, 5 notes: 1. see figure in ?ac test conditions?. 2. parameters may be guaranteed by design, i.e., without tester guardband. 3. transitions are measured 50 mv of output high impedance from output low impedance. 4. transitions are measured 50 mv from steady state voltage. 5. when zz is switching, clock input k must be at the same logic level for the reliable operation. 6. minimum value is verified by design and tested without guardband.
HM64YGB36100 series rev.1.00 jun 27, 2005 page 9 of 19 timing waveforms read cycle-1 k, k q1 q2 ss swe swex dq a2 a3 a4 a1 sa t avkh t khax t avkh t khax t avkh t khax t khqx t khqv t khkh t khkl t klkh read cycle-2 ( ss controlled) k, k a3 a4 a1 sa t avkh t khax t avkh t khax swex ss swe t avkh t khax dq q0 q1 q3 t khqz t khqx2 t khkh t khkl t klkh
HM64YGB36100 series rev.1.00 jun 27, 2005 page 10 of 19 read cycle-3 ( g controlled) q0 q1 q3 a2 a3 a4 a1 sa ss swe swex dq t avkh t khax t avkh t khax t avkh t khax g t ghqz t glqx t glqv k, k t khkh t khkl t klkh read operation during read cycle, the address is registered during the first rising clock edge, the internal array is read between this first edge and second edge, and data is captured in the output register.
HM64YGB36100 series rev.1.00 jun 27, 2005 page 11 of 19 write cycle a2 a3 a4 a1 k, k sa ss swe swex dq t avkh t khax t avkh t khax t avkh t khax g d1 d2 d3 d0 t avkh t khax t dvkh t khdx t khkh t khkl t klkh notes: zz = v il , x: a to d write operation during write cycle, the write data follows the write address by one cycle. all n bits of address are presented during the same cycle. any subsequent read to this address should get the latest data. because in the actual implementation the data will be written into the sram array only after the next write address is received, a one-entry buffer is needed to hold the write data and to allow bypassing of data from the write buffer to the output if there is a read of the same address.
HM64YGB36100 series rev.1.00 jun 27, 2005 page 12 of 19 read-write cycle k, k t khkh t khkl t klkh a6 a7 a3 a4 a1 sa t avkh t khax ss t avkh t khax swe t avkh t khax swex t avkh t khax q0 q1 d3 q4 q6 g t khqv t khqx t ghqz t dvkh t khdx t glqv t glqx t khqz dq read read ( g control) read write dead ( ss control) write notes: zz = v il , x: a to d zz control k, k t khkh t khkl t klkh sa a1 t avkh t khax ss t avkh t khax swex swe t avkh t khax q1 t zzr dq t zze zz sleep active sleep off sleep active notes: g = v il , x: a to d when zz is switching, clock input k must be at the same logic level for the reliable operation.
HM64YGB36100 series rev.1.00 jun 27, 2005 page 13 of 19 input capacitance (v dd = 2.5 v, v ddq = 1.5 v, ta = +25 c, f = 1 mhz) parameter symbol min max unit pin name notes input capacitance c in ? 4 pf san, ss , swe , swex 1, 3 clock input capacitance c clk ? 5 pf k, k 1, 2, 3 i/o capacitance c io ? 5 pf dqxn 1, 3 notes: 1. this parameter is sampled and not 100% tested. 2. exclude g 3. connect pins to gnd, except v dd , v ddq , and the measured pin. ac test conditions parameter symbol conditions unit note input and output timing reference levels v ref 0.75 v input signal amplitude v il , v ih 0.25 to 1.25 v input rise / fall time tr, tf 0.5 (10% to 90%) ns clock input timing reference level differential cross point v dif to clock 0.75 v v cm to clock 0.75 v output loading conditions see figure below note: parameters are tested with rq = 250 ? and v ddq = 1.5 v. output loading conditions 50 ? 16.7 ? 16.7 ? 50 ? 5 pf dq 50 ? 16.7 ? 50 ? 5 pf 0.75 v 0.75 v 0.75 v
HM64YGB36100 series rev.1.00 jun 27, 2005 page 14 of 19 boundary scan test access port operations overview in order to perform the interconnect testing of the modules that include this sram, the serial boundary scan test access port (tap) is designed to operate in a manner consistent with ieee standard 1149.1 - 1990. but does not implement all of the functions required for 1149.1 compliance. the hm64ygb series contains a tap controller. instruction register, boundary scans register, bypass register and id register. test access port pins symbol i/o name tck test clock tms test mode select tdi test data in tdo test data out note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. to disable the tap, tck must be connected to v ss . tdo should be left unconnected. to test boundary scan, the zz pin needs to be kept below v ref ? 0.4 v. tap dc operating characteristics (ta = 0 to +85 c) parameter symbol min max notes boundary scan input high voltage v ih 1.4 v 3.6 v boundary scan input low voltage v il ? 0.3 v 0.8 v boundary scan input leakage current i li ? 10 a +10 a 1 boundary scan output low voltage v ol ? 0.2 v 2 boundary scan output high voltage v oh 2.1 v ? 3 notes: 1. 0 v in 3.6 v for all logic input pin 2. i ol = 2 ma at v dd = 2.5 v. 3. i oh = ? 2 ma at v dd = 2.5 v.
HM64YGB36100 series rev.1.00 jun 27, 2005 page 15 of 19 tap ac operating characteristics (ta = 0 to +85 c) parameter symbol min max unit note test clock cycle time t thth 67 ? ns test clock high pulse width t thtl 30 ? ns test clock low pulse width t tlth 30 ? ns test mode select setup t mvth 10 ? ns test mode select hold t thmx 10 ? ns capture setup t cs 10 ? ns 1 capture hold t ch 10 ? ns 1 tdi valid to tck high t dvth 10 ? ns tck high to tdi don?t care t thdx 10 ? ns tck low to tdo unknown t tlqx 0 ? ns tck low to tdo valid t tlqv ? 20 ns note: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure pad data capture. tap ac test conditions (v dd = 2.5 v) temperature 0 c ta +85 c input timing measurement reference level 1.1 v input pulse levels 0 to 2.5 v input rise/fall time 1.5 ns typical (10% to 90%) output timing measurement reference level 1.25 v test load termination supply voltage (v t ) 1.25 v output load see figure below boundary scan ac test load dut tdo z 0 = 50 ? 50 ? v t
HM64YGB36100 series rev.1.00 jun 27, 2005 page 16 of 19 tap controller timing diagram tck tms tdi tdo ram address t thth t thtl t mvth t thmx t dvth t thdx t tlqv t tlqx t cs t ch t tlth test access port registers register name length symbol note instruction register 3 bits ir [2:0] bypass register 1 bit bp id register 32 bits id [31:0] boundary scan register 70 bits bs [70:1] tap controller instruction set ir2 ir1 ir0 instruction operation 0 0 0 sample-z tristate all data drivers and capture the pad value 0 0 1 idcode 0 1 0 sample-z tristate all data drivers and capture the pad value 0 1 1 bypass 1 0 0 sample 1 0 1 bypass 1 1 0 private do not use. they are reserved for vendor use only 1 1 1 bypass note: this device does not perform extest, intest or the preload portion of the preload command in ieee 1149.1.
HM64YGB36100 series rev.1.00 jun 27, 2005 page 17 of 19 boundary scan order (HM64YGB36100) bit # bump id signal name bit # bump id signal name 1 5r m2 36 3b sa12 2 4p sa19 37 2b sa15 3 4t sa3 38 3a sa13 4 6r sa1 39 3c sa11 5 5t sa2 40 2c sa16 6 7t zz 41 2a sa14 7 6p dqa8 42 2d dqc8 8 7p dqa7 43 1d dqc7 9 6n dqa6 44 2e dqc6 10 7n dqa5 45 1e dqc5 11 6m dqa4 46 2f dqc4 12 6l dqa2 47 2g dqc2 13 7l dqa3 48 1g dqc3 14 6k dqa0 49 2h dqc0 15 7k dqa1 50 1h dqc1 16 5l swea 51 3g swec 17 4l k 52 4d zq 18 4k k 53 4e ss 19 4f g 54 4b sa20 20 5g sweb 55 4h nc 21 7h dqb1 56 4m swe 22 6h dqb0 57 3l swed 23 7g dqb3 58 1k dqd1 24 6g dqb2 59 2k dqd0 25 6f dqb4 60 1l dqd3 26 7e dqb5 61 2l dqd2 27 6e dqb6 62 2m dqd4 28 7d dqb7 63 1n dqd5 29 6d dqb8 64 2n dqd6 30 6a sa7 65 1p dqd7 31 6c sa8 66 2p dqd8 32 5c sa4 67 3t sa18 33 5a sa6 68 2r sa10 34 6b sa9 69 4n sa17 35 5b sa5 70 3r m1 notes: 1. bit#1 is the first scan bit to exit the chip. 2. the nc pads listed in this table are indeed no connects, but are represented in the boundary scan register by a ?place holder?. place holder registers are internally connected to v ss . 3. in boundary scan mode, differential input k and k are referenced to each other and must be at the opposite logic levels for the reliable operation. 4. zz must remain v il during boundary scan. 5. in boundary scan mode, zq must be driven to v ddq or v ss supply rail to ensure consistent results. 6. m1 and m2 must be driven to v dd , v ddq or v ss supply rail to ensure consistent results.
HM64YGB36100 series rev.1.00 jun 27, 2005 page 18 of 19 id register part revision number (31:28) device density and configuration (27:18) vendor definition (17:12) vendor jedec code (11:1) start bit (0) HM64YGB36100 0000 0100000100 xxxxxx 00000000111 1 tap controller state diagram 1 111 0 0 00 00 0 0 0 1 11 11 0 1 11 1 10 10 0 0 0 0 1 test-logic- reset run-test/ idle select- dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select- ir-scan note: the value adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. no matter what the original state of the controller, it will enter test-logic-reset when tms is held high for at least five rising edges of tck.
HM64YGB36100 series rev.1.00 jun 27, 2005 page 19 of 19 package dimensions HM64YGB36100bp series (prbg0119dc-a / previous code: bp-119f) prbg0119dc-a p-bga119-14x22-1.27 d e s s d e z z d e 1.98 1.78 e a max nom min dimension in millimeters symbol reference a b x y 1 14.00 0.20 1.27 0.84 0.90 0.96 0.58 0.66 0.74 2.18 22.00 0.30 v w y0.35 1 0.20 previous code jeita package code renesas code bp-119f 1.0g mass[typ.] u t r p n m l k j h g f e d c b 7 6 5 4 3 2 1 1 a s s y v s y 1 index a b sab s a a e e 0.15 b m 4 m d e
revision history HM64YGB36100 series data sheet description rev. date page summary 0.0 dec. 5, 2002 ? initial issue 1.00 jun. 27, 2005 ? 1 5 19 change format issued by renesas technology corp. ordering information addition of renesas package codes change of programmable impedance output drivers package dimensions addition of renesas package codes changed to renesas formats
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